View XQ18V04CC44M_111373.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

0
R
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
5
DS082 (v1.2) November 5, 2001
0
Preliminary Product Specification
Features
* In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs * * * Endurance of 2,000 program/erase cycles Program/erase over full military temperature range
Radiation Hardenned XQR18V04
* * * * Fabricated on Epitaxial Substrate Latch-Up Immune to >120 LET Guaranteed TID of 40 kRad(Si) Supports SEU Scrubbing
IEEE Std 1149.1 boundary-scan (JTAG) support Cascadable for storing longer or multiple bitstreams Dual configuration modes Serial Slow/Fast configuration (up to 33 MHz) Parallel (up to 264 Mbps at 33 MHz)
Description
Xilinx introduces the QProTM XQ18V04 and XQR18V04 series of QML in-system programmable and radiation hardened configuration PROMs. Initial devices in this 3.3V family are a 4-megabit PROM that provide an easy-to-use, cost-effective method for re-programming and storing large Xilinx FPGA configuration bitstreams. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising CCLK, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock. When the FPGA is in Express or SelectMAP Mode, an external oscillator will generate the configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data are available on the PROMs DATA (D0-D7) pins. The data will be clocked into the FPGA on the following rising edge of the CCLK. Neither Express nor SelectMAP utilize a Length Count, so a free-running oscillator may be used. See Figure 6.
OE/Reset
* * * * * * *
Low-power advanced CMOS FLASH process 5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals. 3.3V or 2.5V output capability Available in CC44 and VQ44 packages. Design support using the Xilinx AllianceTM and FoundationTM series software packages. JTAG command initiation of standard FPGA configuration. Available to Standard Microcircuit Drawing 5962-01525. For more information contact Defense Supply Center Columbus (DSCC) at http://www.dscc.dla.mil
CLK CE
TCK TMS TDI TDO
Control and JTAG Interface
Data Memory Address Data Serial or Parallel Interface
7
CEO D0 DATA (Serial or Parallel [Express/SelectMAP] Mode) D[1:7] Express Mode and SelectMAP Interface
CF
DS026_01_021000
Figure 1: XQ18V04 Series Block Diagram
(c) 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
1
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this
R
chain are interconnected. All devices are compatible and can be cascaded with other members of the family or with the XC1700L one-time programmable Serial PROM family.
Pinout and Pin Description
Table 1: Pin Names and Descriptions (pins not listed are "no connect") Pin Name D0 Boundary Scan Order 4 3 D1 6 5 D2 2 1 D3 8 7 D4 24 23 D5 10 9 D6 17 16 D7 14 13 CLK OE/ RESET 0 20 19 18 CE 15 44-pin Function DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA IN DATA IN DATA OUT OUTPUT ENABLE DATA IN Each rising edge on the CLK input increments the internal address counter if both CE is Low and OE/RESET is High. When Low, this input holds the address counter reset and the DATA output is in a high-impedance state. This is a bidirectional open-drain pin that is held Low while the PROM is reset. Polarity is NOT programmable. When CE is High, this pin puts the device into standby mode and resets the address counter. The DATA output pin is in a high-impedance state, and the device is in low power standby mode. 43 13 5 19 19 25 14 20 25 31 9 15 27 33 Pin Description D0 is the DATA output pin to provide data for configuring an FPGA in serial mode. VQFP 40 44-pin CLCC 2
D0-D7 are the output pins to provide parallel data for configuring a Xilinx FPGA in Express/SelectMap mode.
29
35
42
4
15
21
2
www.xilinx.com 1-800-255-7778
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
R
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
Table 1: Pin Names and Descriptions (pins not listed are "no connect") (Continued) Pin Name CF Boundary Scan Order 22 21 44-pin Function DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE Pin Description Allows JTAG CONFIG instruction to initiate FPGA configuration without powering down FPGA. This is an open-drain output that is pulsed Low by the JTAG CONFIG command. Chip Enable Output (CEO) is connected to the CE input of the next PROM in the chain. This output is Low when CE is Low and OE/RESET input is High, AND the internal address counter has been incremented beyond its Terminal Count (TC) value. When OE/RESET goes Low, CEO stays High until the PROM is brought out of reset by bringing OE/RESET High. GND is the ground connection. VQFP 10 44-pin CLCC 16
CEO
13 14
21
27
GND
6, 18, 28 & 41 5
3, 12, 24 & 34 11
TMS
MODE SELECT
The state of TMS on the rising edge of TCK determines the state transitions at the Test Access Port (TAP) controller. TMS has an internal 50K ohm resistive pull-up on it to provide a logic "1" to the device if the pin is not driven. This pin is the JTAG test clock. It sequences the TAP controller and all the JTAG test and programming electronics. This pin is the serial input to all JTAG instruction and data registers. TDI has an internal 50K ohm resistive pull-up on it to provide a logic "1" to the system if the pin is not driven. This pin is the serial output for all JTAG instruction and data registers. TDO has an internal 50K ohm resistive pull-up on it to provide a logic "1" to the system if the pin is not driven. Positive 3.3V supply voltage for internal logic and input buffers. Positive 3.3V or 2.5V supply voltage connected to the output voltage drivers.
TCK
CLOCK
7
13
TDI
DATA IN
3
9
TDO
DATA OUT
31
37
VCC VCCO
17, 35 & 38 8, 16, 26 & 36
23, 41 & 44 14, 22, 32 & 42
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
3
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
R
Xilinx FPGAs and Compatible PROMs
Device XQV100 XQV(R)300 XQV(R)600 XQV(R)1000 XQV(R)600E XQV(R)1000E XQV(R)2000E Configuration Bits 781,216 1,751,808 3,607,968 6,127,744 3,961,632 6,587,520 10,159,648 XQ(R)18VO4 PROMs 1 1 1 2 1 2 3
In-System Programming
In-System Programmable PROMs can be programmed individually, or two or more can be daisy-chained together and programmed in-system via the standard 4-pin JTAG protocol as shown in Figure 2. In-system programming offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices. The Xilinx development system provides the programming data sequence using either Xilinx JTAG Programmer software and a download cable, a third-party JTAG development system, a JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction sequence. The JTAG Programmer software also outputs serial vector format (SVF) files for use with any tools that accept SVF format and with automatic test equipment. All outputs are held in a high-impedance state or held at clamp levels during in-system programming.
Capacity
Devices XQ(R)18V04 Configuration Bits 4,194,304
OE/RESET
The ISP programming algorithm requires issuance of a reset that will cause OE to go Low.
External Programming
Xilinx reprogrammable PROMs can also be programmed by the Xilinx HW-130 device programmer. This provides the added flexibility of using pre-programmed devices in board design and boundary-scan manufacturing tools, with an in-system programmable option for future enhancements and design changes.
Reliability and Endurance
Xilinx in-system programmable products provide a guaranteed endurance level of 2,000 in-system program/erase cycles and a minimum data retention of ten years. Each device meets all functional, performance, and data retention specifications within this endurance limit.
Design Security
The Xilinx in-system programmable PROM devices incorporate advanced data security features to fully protect the programming data against unauthorized reading. Table 2 shows the security setting available. The read security bit can be set by the user to prevent the internal programming pattern from being read or copied via JTAG. When set, it allows device erase. Erasing the entire device is the only way to reset the read security bit. Table 2: Data Security Options Default = Reset Read Allowed Program/Erase Allowed Set Read Inhibited via JTAG Erase Allowed
4
www.xilinx.com 1-800-255-7778
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
R
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
V CC
GND
(a)
(b)
DS026_02_011100
Figure 2: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
IEEE 1149.1 Boundary-Scan (JTAG)
The XQ(R)18V04 family is fully compliant with the IEEE Std. 1149.1 Boundary-Scan, also known as JTAG. A Test Access Port (TAP) and registers are provided to support all required boundary scan instructions, as well as many of the optional instructions specified by IEEE Std. 1149.1. In addition, the JTAG interface is used to implement in-system programming (ISP) to facilitate configuration, erasure, and verification operations on the XQ(R)18V04 device. Table 3 lists the required and optional boundary-scan instructions supported in the XQ(R)18V04. Refer to the IEEE Std. 1149.1 specification for a complete description of boundary-scan architecture and the required and optional instructions.
Table 3: Boundary Scan Instructions Boundary-Scan Command Binary Code [7:0] Description
Required Instructions BYPASS SAMPLE/ PRELOAD EXTEST 11111111 00000001 Enables BYPASS Enables boundary-scan SAMPLE/PRELOAD operation Enables boundary-scan EXTEST operation
00000000
Optional Instructions CLAMP HIGHZ 11111010 11111100 Enables boundary-scan CLAMP operation All outputs in high-impedance state simultaneously Enables shifting out 32-bit IDCODE Enables shifting out 32-bit USERCODE
IDCODE USERCODE
11111110 11111101
XQ(R)18V04 Specific Instructions CONFIG 11101110 Initiates FPGA configuration by pulsing CF pin Low
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
5
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
R
Instruction Register
The Instruction Register (IR) for the XQ(R)18V04 is eight bits wide and is connected between TDI and TDO during an instruction scan sequence. In preparation for an instruction scan sequence, the instruction register is parallel loaded with a fixed instruction capture pattern. This pattern is shifted out onto TDO (LSB first), while an instruction is shifted into the instruction register from TDI. The detailed composition of the instruction capture pattern is illustrated in Figure 3. The ISP Status field, IR(4), contains logic "1" if the device is currently in ISP mode; otherwise, it will contain logic "0". The Security field, IR(3), will contain logic "1" if the device has been programmed with the security option turned on; otherwise, it will contain logic "0".
IR[7:5] TDI-> Notes: 000 IR[4] ISP Status IR[3] Security IR[2] 0 IR[1:0] 01 ->TDO
tion by using the IDCODE instruction. The IDCODE is available to any other system component via JTAG. The IDCODE register has the following binary format: vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1 where v = the die version number f = the family code (50h for XQ(R)18V04 family) a = the ISP PROM product ID (26h for the XQ(R)18V04) c = the company code (49h for Xilinx) Note: The LSB of the IDCODE register is always read as logic "1" as defined by IEEE Std. 1149.1 Table 4 lists the IDCODE XQ(R)18V00 devices. 0 register values for the
Table 4: IDCODES Assigned to XQ(R)18V04 Devices ISP-PROM XQ(R)18V04 IDCODE 05026093h
1. IR(1:0) = 01 is specified by IEEE Std. 1149.1 Figure 3: Instruction Register Values Loaded into IR as Part of an Instruction Scan Sequence
Boundary Scan Register
The boundary-scan register is used to control and observe the state of the device pins during the EXTEST, SAMPLE/PRELOAD, and CLAMP instructions. Each output pin on the XQ(R)18V00 has two register stages that contribute to the boundary-scan register, while each input pin only has one register stage. For each output pin, the register stage nearest to TDI controls and observes the output state, and the second stage closest to TDO controls and observes the High-Z enable state of the pin. For each input pin, the register stage controls and observes the input state of the pin. Identification Registers The IDCODE is a fixed, vendor-assigned value that is used to electrically identify the manufacturer and type of the device being addressed. The IDCODE register is 32 bits wide. The IDCODE register can be shifted out for examina-
The USERCODE instruction gives access to a 32-bit user programmable scratch pad typically used to supply information about the device's programmed contents. By using the USERCODE instruction, a user-programmable identification code can be shifted out for examination. This code is loaded into the USERCODE register during programming of the XQ(R)18V04 device. If the device is blank or was not loaded during programming, the USERCODE register will contain FFFFFFFFh.
XQ(R)18V04 TAP Characteristics
The XQ(R)18V04 family performs both in-system programming and IEEE 1149.1 boundary-scan (JTAG) testing via a single 4-wire Test Access Port (TAP). This simplifies system designs and allows standard Automatic Test Equipment to perform both functions. The AC characteristics of the XQ(R)18V04 TAP are described as follows.
TAP Timing
Figure 4 shows the timing relationships of the TAP signals. These TAP timing characteristics are identical for both boundary-scan and ISP operations.
6
www.xilinx.com 1-800-255-7778
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
R
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
TCKMIN
TCK
TMSS TMSH
TMS
TDIS TDIH
TDI
TDOV
TDO
DS026_04_020300
Figure 4: Test Access Port Timing
TAP AC Parameters
Table 5 shows the timing parameters for the TAP waveforms shown in Figure 4 Table 5: Test Access Port Timing Parameters Symbol TCKMIN1 TCKMIN2 TMSS TMSH TDIS TDIH TDOV Parameter TCK minimum clock period TCK minimum clock period, Bypass mode TMS setup time TMS hold time TDI setup time TDI hold time TDO valid delay Min 100 50 10 25 10 25 Max 25 Units ns ns ns ns ns ns ns
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
7
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
R
Connecting Configuration PROMs
Connecting the FPGA device with the configuration PROM (see Figure 6). * * * * The DATA output(s) of the PROM(s) drives the DIN input of the lead FPGA device. The Master FPGA CCLK output drives the CLK input(s) of the PROM(s) (in Master Serial mode only). The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). The OE/RESET input of all PROMs is best driven by the INIT output of the lead FPGA device. This connection assures that the PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. The PROM CE input can be driven from the DONE pin. The CE input of the first (or only) PROM can be driven by the DONE output of the first FPGA device, provided that DONE is not permanently grounded. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 20 mA maximum. Express/SelectMap mode is similar to slave serial mode. The DATA is clocked out of the PROM one byte per CCLK instead of one bit per CCLK cycle. See FPGA data sheets for special configuration requirements.
JTAG Programmer software. Serial output is the default programming mode.
Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration program from an external memory. Xilinx PROMs are designed to accommodate the Master Serial mode. Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA mode-select pins are Low (M0=0, M1=0, M2=0). Data is read from the PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated by the FPGA during configuration. Master Serial Mode provides a simple configuration interface. Only a serial data line, a clock line, and two control lines are required to configure an FPGA. Data from the PROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK. If the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. The Xilinx FPGA families take care of this automatically with an on-chip pull-up resistor.
*
*
Initiating FPGA Configuration
The XQ(R)18V04 devices incorporate a pin named CF that is controllable through the JTAG CONFIG instruction. Executing the CONFIG instruction through JTAG pulses the CF low for 300-500 ns, which resets the FPGA and initiates configuration. The CF pin must be connected to the PROGRAM pin on the FPGA(s) to use this feature. The JTAG Programmer software can also issue a JTAG CONFIG command to initiate FPGA configuration through the "Load FPGA" setting.
Cascading Configuration PROMs
For multiple FPGAs configured as a serial daisy-chain, or a single FPGA requiring larger configuration memories in a serial or SelectMAP configuration mode, cascaded PROMs provide additional memory (Figure 5). Multiple XQ(R)18V04 devices can be concatenated by using the CEO output to drive the CE input of the downstream device. The clock inputs and the data outputs of all XQ(R)18V04 devices in the chain are interconnected. After the last bit from the first PROM is read, the next clock signal to the PROM asserts its CEO output Low and drives its DATA line to a high-impedance state. The second PROM recognizes the Low level on its CE input and enables its DATA output. See Figure 6. After configuration is complete, the address counters of all cascaded PROMs are reset if the PROM OE/RESET pin goes Low.
Selecting Configuration Modes
The XQ(R)18V04 accommodates serial and parallel methods of configuration. The configuration modes are selectable through a user control register in the XQ(R)18V04 device. This control register is accessible through JTAG, and is set using the "Parallel mode" setting on the Xilinx
8
www.xilinx.com 1-800-255-7778
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
R
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
Vcc
Vcco
Vcc
Vcco
Vcc 4.7K Vcc DIN MODE PINS* DOUT Vcc DIN MODE PINS*
Vcc Vcco
D0
Vcc Vcco
D0
Xilinx FPGA
Vcc
Xilinx FPGA Slave Serial
XC18V00 Cascaded PROM
1 2 3 4 TDI TMS TCK CLK CE CEO OE/RESET CF GND TDO GND TDI TMS TCK
XC18V00 First PROM
CLK CE CEO OE/RESET CF TDO
Master Serial
J1
TDI TMS TCK TDO
**
CCLK DONE INIT PROGRAM TDI TMS TCK TDO CCLK DONE INIT PROGRAM TDI TMS TCK TDO
* For Mode pin connections, refer to appropriate FPGA data sheet. ** Virtex, Virtex-E is 300 ohms, all others are 4.7K.
DS026_08_021000
Figure 5: JTAG Chain for Configuring Devices in Master Serial Mode
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
9
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
R
DOUT
OPTIONAL Daisy-chained FPGAs with different configurations VCC 4.7K VCC OPTIONAL Slave FPGAs with identical configurations Vcco Vcc
FPGA
Modes*
**
VCC VCCO DATA First CLK PROM CEO CE OE/RESET CF
DIN CCLK DONE INIT PROGRAM
DATA CLK CE OE/RESET CF Cascaded PROM
(Low Resets the Address Pointer) *For Mode pin connections, refer to the appropriate FPGA data sheet. **Virtex, Virtex-E is 300 ohms, all others are 4.7K.
Master Serial Mode
I/O* I/O* Modes*** CS WRITE 1K 1K VCC External Osc 3.3V 4.7K XC18Vxx CLK 8 D[0:7] CE OE/RESET CEO CF VCC VCCO VCC VCCO
VIRTEX Select MAP NC BUSY CCLK PROGRAM D[0:7] DONE INIT
**
*CS and WRITE must be pulled down to be used as I/O. One option is shown. **Virtex, Virtex-E is 300 ohms, all others are 4.7K. ***For Mode pin connections, refer to the appropriate FPGA data sheet.
Virtex Select MAP Mode
To Additional Optional Daisy-chained Devices
VCC VCC 4.7K VCC VCCO D[0:7] CEO XC18Vxx CE CF PROGRAM DONE INIT CCLK 8 4.7K VCC VCCO VCC M0 CS1 M1 DOUT M0 CS1 M1
Spartan-XL, XC4000 D[0:7]
DOUT Optional Daisy-chained Spartan-XL, XC4000 D[0:7]
PROGRAM DONE INIT CCLK To Additional Optional Daisy-chained Devices
OE/RESET CLK
External Osc
Spartan-XL Express Mode
DS026_05_031000
Figure 6: (a) Master Serial Mode (b) Virtex Select MAP Mode (c) Spartan-XL Express Mode (dotted lines indicates optional connection)
10 www.xilinx.com 1-800-255-7778 DS082 (v1.2) November 5, 2001 Preliminary Product Specification
R
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs is held low until the XQ(R)18V04 voltage reaches the operating voltage range. If the power drops below 2.0V, the PROM will reset. OE/RESET polarity is NOT programmable.
5V Tolerant I/Os
The I/Os on each re-programmable PROM are fully 5V tolerant even through the core power supply is 3.3V. This allows 5V CMOS signals to connect directly to the PROM inputs without damage. In addition, the 3.3V VCC power supply can be applied before or after 5V signals are applied to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins, the core power supply (VCC), and the output power supply (VCCO) may have power applied in any order. This makes the PROM devices immune to power supply sequencing issues.
Standby Mode
The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high-impedance state regardless of the state of the OE input. JTAG pins TMS, TDI and TDO can be in a high-impedance state or High.
Reset Activation
On power up, OE/RESET is held low until the XQ(R)18V04 is active (1 ms) and able to supply data after receiving a CCLK pulse from the FPGA. OE/RESET is connected to an external resistor to pull OE/RESET HIGH releasing the FPGA INIT and allowing configuration to begin. OE/RESET Table 6: Truth Table for PROM Control Inputs Control Inputs OE/RESET High Low High Low CE Low Low High High Internal Address
Customer Control Pins
The XQ(R)18V04 PROMs have various control bits accessible by the customer. These can be set after the array has been programmed using "Skip User Array" in Xilinx JTAG Programmer Software.
Outputs DATA Active High-Z High-Z High-Z High-Z CEO High Low High High High ICC Active Reduced Active Standby Standby
If address < TC(1): increment If address > TC (1): don't change Held reset Held reset Held reset
Notes: 1. TC = Terminal Count = highest address value. TC + 1 = address 0.
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
11
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
R
Absolute Maximum Ratings(1,2)
Symbol VCC VIN VTS TSTG TJ Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to High-Z output Storage temperature (ambient) Junction temperature Ceramic Plastic Value -0.5 to +4.0 -0.5 to +5.5 -0.5 to +5.5 -65 to +150 +150 +125 Units V V V C C C
Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less then 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operating Conditions
Symbol VCCINT Parameter Internal voltage supply (TC = -55C to +125C) Internal voltage supply (TJ = -55C to +125C) VCCO Supply voltage for output drivers for 3.3V operation Supply voltage for output drivers for 2.5V operation VIL VIH VO Low-level input voltage High-level input voltage Output voltage Ceramic Plastic Min 3.0 3.0 3.0 2.3 0 2.0 0 Max 3.6 3.6 3.6 2.7 0.8 5.5 VCCO Units V V V V V V V
Quality and Reliability Characteristics
Symbol TDR NPE VESD Data retention Program/erase cycles (Endurance) Electrostatic discharge (ESD) Description Min 10 2,000 2,000 Max Units Years Cycles Volts
Radiation Tolerances for XQR18V04
Symbol TID SEL Total Ionizing Dose Single Event Latch-Up (No Latch-Up observed for LET > 120 MeV-mg/cm2) SEU Static Memory Cell Saturation Bit Cross-Section (No Upset observed for LET > 120 MeV-mg/cm2) 0 cm2 Description Min Max 40 0 Units krad(Si) cm2
12
www.xilinx.com 1-800-255-7778
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
R
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
DC Characteristics Over Operating Conditions
Symbol VOH Parameter High-level output voltage for 3.3V outputs High-level output voltage for 2.5V outputs VOL Low-level output voltage for 3.3V outputs Low-level output voltage for 2.5V outputs ICC ICCS IILJ IIL IIH CIN and COUT Supply current, active mode Supply current, standby mode JTAG pins TMS, TDI, and TDO Input leakage current Input and output High-Z leakage current Input and output capacitance VCC = MAX VIN = GND VCC = Max VIN = GND or VCC VCC = Max VIN = GND or VCC VIN = GND f = 1.0 MHz Test Conditions IOH = -4 mA IOH = -500 A IOL = 8 mA IOL = 500 A 25 MHz Min 2.4 90% VCCO -100 -10 -10 Max 0.4 0.4 50 20 10 10 10 Units V V V V mA mA A A A pF
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
13
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
.AC
R
Characteristics Over Operating Conditions for XC18V04
CE
TSCE
.
THCE
OE/RESET
TLC THC TCYC THOE
CLK
TOE TCE TCAC TOH TDF
DATA
TOH
DS026_06_012000
Symbol TOE TCE TCAC TOH TDF TCYC TLC THC TSCE THCE THOE OE/RESET to data delay CE to data delay CLK to data delay
Description
Min 0 50 10 10 25 2 25
Max 10 20 20 25 -
Units ns ns ns ns ns ns ns ns ms s ns
Data hold from CE, OE/RESET, or CLK CE or OE/RESET to data float delay(2) Clock periods CLK Low time(3) CLK High time(3) CE setup time to CLK (to guarantee proper counting)(3) CE High time (to guarantee proper counting) OE/RESET hold time (guarantees counters are reset)
Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 5. If THCE High < 2 s, TCE = 2 s.
14
www.xilinx.com 1-800-255-7778
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
R
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
AC Characteristics Over Operating Conditions When Cascading for XC18V04
OE/RESET
CE
CLK
TCDF TOCE First Bit TOOE
DATA
Last Bit TOCK
CEO
DS026_07_020300
Symbol TCDF TOCK TOCE TOOE
Description CLK to data float delay(2,3) CLK to CEO delay(3) CE to CEO delay(3) OE/RESET to CEO delay(3)
Min -
Max 25 20 20 20
Units ns ns ns ns
Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
15
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
R
Ordering Information
XQ18V04 CC44 V
Device Number Package Type Grade (Manufacturing Flow / Temperature Range)
Device Ordering Options
Device Type XQ18V04 XQR18V04(1) CC44 VQ44 Package 44-pin Ceramic Chip Carrier Package 44-pin Plastic Thin Quad Flat Package Grade
M N V
Military Ceramic Military Plastic QPro-Plus
TC = -55C to +125C TJ = -55C to +125C TC = -55C to +125C
Notes: 1. Radiation Hardened.
5962 - 01525 Q Y A
Generic Standard Microcircuit Drawing (SMD) Lead Finish Package Type Radiation Hardened (1) Device Type QML Certified MIL-PRF-38535
SMD Ordering Options
Device Type 5962-01525 5962R01525 XQ18V04 XQR18V04 QML Package 44-pin Ceramic Chip Carrier Package 44-pin Plastic Thin Quad Flat Package Lead Finish Solder Dip Solder Plate
Notes: 1. Type R designates Radiation Hardened.
Valid Ordering Combinations
Mil-Std XQ18V04CC44M XQ18V04VQ44N SMD
-
Rad Hard XQR18V04CC44M XQR18V04CC44V
SMD
-
16
www.xilinx.com 1-800-255-7778
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
R
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
Revision History
The following table shows the revision history for this document. Date 5/1/01 7/23/01 11/05/01 Version 1.0 1.1 1.2 Revision First publication of this early access specification Preliminary publication supporting Full Mil Temp range and corrected write cycles Added Class V to ordering combinations for Rad Hard version. Updated format.
DS082 (v1.2) November 5, 2001 Preliminary Product Specification
www.xilinx.com 1-800-255-7778
17
This datasheet has been download from: www..com Datasheets for electronics components.

▲Up To Search▲

Price & Availability of XQ18V04CC44M

	To Download XQ18V04CC44M Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .